A Design and Analysis of Low Power Linear Feedback Shift Register with Clock Gating
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چکیده
This paper presents a method to reduce the power consumption of the popular linear feedback shift register. The proposed scheme is based on the gated clock design approach and it can offer a significant power reduction, depending on technological characteristics of the employed gates. A modified Linear Feedback Shift Register is designed in which power consumption is reduced by deactivating the clock signal to Flip Flop when the output signal is not different from input signal. The power consumption of the new LFSR is reduced due to the reduced switching of Flip Flop To verify, the maximum, minimum and average power of the two LFSRs are the compared.
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